Sr FPGA Design/Verification Engineer

Hazelwood, Missouri
Industry: Database Administrator / Engineers
Job Number: JN -062021-65009

JOB DESCRIPTION

Leads analysis of customer and system requirements and development of architectural approaches and detailed specifications for various electronic products.

Leads development of high-level and detailed designs consistent with requirements and specifications.

Leads reviews of testing and analysis activity to assure compliance to requirements.

Identifies, tracks and statuses technical performance measures to measure progress and ensure compliance with requirements.

Leads activities in support of Supplier Management with make/buy recommendations and other technical services.

Coordinates engineering support throughout the lifecycle of the product.

Plans research projects to develop concepts for future product designs to meet projected requirements.

Works under minimal direction.

Leads activities to develop, document and maintain complex architectures, requirements, algorithms, interfaces and designs for Xilinx FPGA based firmware systems.

Leads development of code and integration of complex firmware components into a fully functional system.

Develops firmware verification plans, test procedures and test environments, executing the test procedures and documenting test results to ensure firmware system requirements are met.

Provides technical leadership for firmware projects.

Leads development, selection, tailoring and deployment of processes, tools and metrics.

Leads firmware research and development projects.

Serves as a subject matter expert for firmware domains, system-specific issues, processes and regulations.

Tracks and evaluates firmware team performance to ensure product and process conformance to project plans and industry standards.


Basic Qualifications (Required Skills/Experience)

Bachelor Degree or higher in Engineering, Mathematics or Physics

6+ years’ of experience in Digital FPGA verification, with design experience

Verification work experience using Verilog or SystemVerilog, with UVM methodology


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