Job Title: Senior Verification Engineer
Location: Remote
Job Summary: We are supporting a confidential opportunity for a Senior Verification Engineer focused on complex ASIC and SoC verification for a highly ambitious silicon program. This position offers the chance to help shape verification strategy, infrastructure, and sign-off methodology across IP, subsystem, and full SoC development.
Responsibilities:
- Own verification planning and execution for complex blocks and subsystems, from test plan through sign-off.
- Translate design specifications into verification strategies, measurable coverage goals, and early risk identification.
- Develop verification environments, reference models, scoreboards, protocol monitors, coverage components, and assertions.
- Drive functional coverage closure, regression health, and sign-off readiness across simulation and formal results.
Required:
- Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field, or 7+ years equivalent experience.
- Minimum five years of professional experience in ASIC or SoC functional verification.
- Hands-on expertise in SystemVerilog, UVM or formal testbench development and maintenance.
- Experience with metric-driven verification for planning, assertions, and functional coverage closure.
- Experience verifying complex digital control and datapath logic, including RTL and system-level debug.
- Background in space-based communications, wireless communications, or modem, baseband, or DSP hardware is preferred.
- Experience verifying LDPC, FEC, framing, or beamforming logic using bit-accurate reference models and fixed-point analysis is preferred.
- Formal verification experience on production silicon, including connectivity, register maps, arbitration, CDC, or security properties is preferred.
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